/*
 * Copyright (c) 2006-2018, RT-Thread Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2020-11-20     liuduanfei   the first version
 */

#include <board.h>
#include "sd.h"
#include <board.h>

int main(void)
{
    IOMUXC_SetPinMux(IOMUXC_SNVS_SNVS_TAMPER3_GPIO5_IO03, 0U);
	
    GPIO5->GDIR |= (1<<3);

	while(1)
	{
		GPIO5->DR &= ~(1<<3);
		rt_thread_mdelay(1000);
		GPIO5->DR |= (1<<3);
		rt_thread_mdelay(1000);
	}

	return 0;
}

void init_pins(void)
{
	/* led pins start */
    IOMUXC_SetPinMux(IOMUXC_SNVS_SNVS_TAMPER3_GPIO5_IO03, 0U);
    IOMUXC_SetPinConfig(IOMUXC_SNVS_SNVS_TAMPER3_GPIO5_IO03, 
                        IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
                        IOMUXC_SW_PAD_CTL_PAD_DSE(1U) |
                        IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	/* led pins end */

	/* uart1 pins start*/	
	IOMUXC_SetPinMux(IOMUXC_UART1_RX_DATA_UART1_RX, 0U);
	IOMUXC_SetPinConfig(IOMUXC_UART1_RX_DATA_UART1_RX, 
						IOMUXC_SW_PAD_CTL_PAD_DSE(2U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK);
	IOMUXC_SetPinMux(IOMUXC_UART1_TX_DATA_UART1_TX, 0U);
	IOMUXC_SetPinConfig(IOMUXC_UART1_TX_DATA_UART1_TX, 
						IOMUXC_SW_PAD_CTL_PAD_DSE(2U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK);
	/* uart1 pins end*/

	/* uSDHC1 pins start*/
	IOMUXC_SetPinMux(IOMUXC_UART1_RTS_B_USDHC1_CD_B, 0U);
    IOMUXC_SetPinConfig(IOMUXC_UART1_RTS_B_USDHC1_CD_B, 
                        IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
                        IOMUXC_SW_PAD_CTL_PAD_DSE(1U) |
                        IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_SD1_CLK_USDHC1_CLK, 0U);
	IOMUXC_SetPinConfig(IOMUXC_SD1_CLK_USDHC1_CLK, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(1U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(1U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_SD1_CMD_USDHC1_CMD, 0U);
	IOMUXC_SetPinConfig(IOMUXC_SD1_CMD_USDHC1_CMD, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(1U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_SD1_DATA0_USDHC1_DATA0, 0U);
	IOMUXC_SetPinConfig(IOMUXC_SD1_DATA0_USDHC1_DATA0, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(1U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_SD1_DATA1_USDHC1_DATA1, 0U);
	IOMUXC_SetPinConfig(IOMUXC_SD1_DATA1_USDHC1_DATA1, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(1U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_SD1_DATA2_USDHC1_DATA2, 0U);
	IOMUXC_SetPinConfig(IOMUXC_SD1_DATA2_USDHC1_DATA2, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(1U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_SD1_DATA3_USDHC1_DATA3, 0U);
	IOMUXC_SetPinConfig(IOMUXC_SD1_DATA3_USDHC1_DATA3, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(1U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	/* uSDHC1 pins end*/

	/* uSDHC2 pins start*/
	IOMUXC_SetPinMux(IOMUXC_NAND_WE_B_USDHC2_CMD, 0U);
	IOMUXC_SetPinConfig(IOMUXC_NAND_WE_B_USDHC2_CMD, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(7U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_NAND_RE_B_USDHC2_CLK, 0U);
	IOMUXC_SetPinConfig(IOMUXC_NAND_RE_B_USDHC2_CLK, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(1U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_NAND_ALE_USDHC2_RESET_B, 0U);
	IOMUXC_SetPinConfig(IOMUXC_NAND_ALE_USDHC2_RESET_B, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(1U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_NAND_DATA00_USDHC2_DATA0, 0U);
	IOMUXC_SetPinConfig(IOMUXC_NAND_DATA00_USDHC2_DATA0, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(7U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_NAND_DATA01_USDHC2_DATA1, 0U);
	IOMUXC_SetPinConfig(IOMUXC_NAND_DATA01_USDHC2_DATA1, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(7U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_NAND_DATA02_USDHC2_DATA2, 0U);
	IOMUXC_SetPinConfig(IOMUXC_NAND_DATA02_USDHC2_DATA2, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(7U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_NAND_DATA03_USDHC2_DATA3, 0U);
	IOMUXC_SetPinConfig(IOMUXC_NAND_DATA03_USDHC2_DATA3, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(7U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_NAND_DATA04_USDHC2_DATA4, 0U);
	IOMUXC_SetPinConfig(IOMUXC_NAND_DATA04_USDHC2_DATA4, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(7U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_NAND_DATA05_USDHC2_DATA5, 0U);
	IOMUXC_SetPinConfig(IOMUXC_NAND_DATA05_USDHC2_DATA5, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(7U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_NAND_DATA06_USDHC2_DATA6, 0U);
	IOMUXC_SetPinConfig(IOMUXC_NAND_DATA06_USDHC2_DATA6, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(7U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(7U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);
	IOMUXC_SetPinMux(IOMUXC_NAND_DATA07_USDHC2_DATA7, 0U);
	IOMUXC_SetPinConfig(IOMUXC_NAND_DATA07_USDHC2_DATA7, 
						IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_DSE(7U) |
						IOMUXC_SW_PAD_CTL_PAD_SPEED(2U) |
						IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
						IOMUXC_SW_PAD_CTL_PAD_PUS(1U) |
						IOMUXC_SW_PAD_CTL_PAD_HYS_MASK);


	/* uSDHC2 pins end*/

}

static unsigned char sd_read_buf[4096];

void sd_test(void)
{
	int i;
	init_pins();

	sd_init(USDHC1);
	
	rt_memset(sd_read_buf, 0x55, sizeof(sd_read_buf));
	sd_write_blocks(USDHC1, sd_read_buf, 4, 1);
	rt_memset(sd_read_buf, 0xAA, sizeof(sd_read_buf));
	sd_write_blocks(USDHC1, sd_read_buf, 5, 1);
	rt_memset(sd_read_buf, 0xBB, sizeof(sd_read_buf));
	sd_write_blocks(USDHC1, sd_read_buf, 6, 3);
	
	rt_memset(sd_read_buf, 0, sizeof(sd_read_buf));
	sd_read_blocks(USDHC1, sd_read_buf, 4, 5);
	for(i = 0; i <512*5; i++) {
		rt_kprintf("%02x ", sd_read_buf[i]);
		if((i + 1)%16 == 0)
			rt_kprintf("\r\n");
	}
	rt_kprintf("\r\n");

}
MSH_CMD_EXPORT(sd_test, ...);

